티스토리 뷰
Precise shared cache analysis using optimal interference placement
Kartik Nagar, Y.N. Srikant
Dept. of Computer Science and Automation,
Indian Institute of Science,
Abstract : Determining the Worst Case Execution Time (WCET) of programs running on a multi-core architecture is a challenging problem, 이것은 멀티코어가 리얼타임 시스템에서 사용되는 것을 방해하고 있다.
The main difficulty in analyzing programs running on multi-core architectures arises from the fact that interferences to shared resources (such as shared cache) from other cores can occur at any time. Hence, to perform safe micro-architectural analysis, current approaches assume that all interferences occur at all times, which results in significantly imprecise analysis WCET estimates.
In our work, we formulate a ILP problem to determine these worst case interference points, from the perspective of a shared cache, and determine the WCET by assuming that the interferences come at those program points.